Encoding
network

ABSTRACT

D R A W I N G 1. IN A SYSTEM HAVING A MEMORY FOR STORING A PLURALITY OF PROGRAM AND DATA WORDS, APPARATUS RESPONSIVE TO SIGNALS FROM SAID MEMORY FOR STORING FOR DETECTING AN ERROR IN THE CONTENT OR SEQUENCING OF A PLURALITY OF SAID WORDS ACCESSED FROM SAID MEMORY COMPRISING: (A) MEANS FOR GENERATING FOR (EACH) A GIVEN WORD STORED IN SAID MEMORY A FIRST CODE WORD REPRESENTATIVE OF THE INFORMATION CONTENT OF (THAT) SAID GIVEN WORD, AND OF THE LOCATION AT WHICH (THAT SAID GIVEN WORD IS STORED IN SAID MEMORY AND OF THE LOCATION OF A DIFFERENT WORD DESIRED TO BE ACCESSED IN ACCORDANCE WITH A PREDETERMINED ORDERED RELATIONSHIP TO (THAT) SAID GIVEN WORD, (B) MEANS FOR STORING SAID FIRST CODE WORDS, (C) MEANS FOR RETRIEVING THE CODE WORD ASSOCIATED WITH A GIVEN PROGRAM OR DATA WORD UPON THE ACCESSING OF SAID GIVE WORD, (D) MEANS FOR GENERATING FOR THE PROGRAM OR DATA WORD MOST RECENTLY ACCESSED FROM SAID MEMORY A SECOND CODE WORD REPRESENTATIVE OF THE INFORMATION CONTENT OF (THAT) SAID MOST RECENTLY ACCESSED WORD, AND OF THE LOCATION FROM WHICH (THAT) SAID MOST RECENTLY ACCESSED WORD WAS ACCESSED, AND OF THE LOCATION FROM WHICH A WORD BEARING SAID PREDETERMINED ORDERED RELATIONSHIP TO SAID MOST RECENTLY ACCESSED WORD WAS ACCESSED, AND (E) MEANS FOR GENERATING AN ERROR SIGNAL WHENEVER THE FIRST AND SECOND CODE WORDS ASSOCIATED WITH AN ACCESSED WORD DO NOT BEAR A PREDETERMINED RELATIONSHIP TO EACH OTHER.

Y 1975 D. M. ROUSE Re. 28,421

MEMORY comma 'rncrmmum Original Filed July 26, 1971 2 Sheets-Sheet 1FIG. 40 SOURCE INF R MATION ENCODING SGNALS NETWORK l PAST/3 UNITGENERATOR GENERATOR F/GZ 2o ACCESSING MEMORY CIRCUIT UNIT eo figgwggCOMPARATOR ERROR INDICATIQN F/G.3 SEQUENCE x \SEQUENCE v CONDITIONALBRANCH CONVERGING BRANCH POINT United States Patent Re. 28,421 RelissuedMay 20, 1975 28 421 MEMORY CODING TECHNIQUE David Michael Rouse,Coiurnbus, Ohio, assignor to Bell Telephone Laboratories, Incorporated,Murray Hill,

Original No. 3,719,815, dated Mar. 6, 1973, Ser. No. 166,130, July 26,1971. Application for reissue May 2, 1974, Ser. No. 466,380

Int. Cl. Gtlfif 11/00; Gllc 29/00 US. Cl. 235153 AM 8 Claims Matterenclosed in heavy brackets appears in the original patent but forms nopart of this reissue specification; matter printed in italics indicatesthe additions made by reissue.

ABSTRACT OF THE DISCLOSURE The present invention includes apparatus forgenerating a first set of check signals encoding not only the addressand information bits of a selected word stored in the memory of a storedprogram machine, but also the address of a preceding word, which may bea transfer word directing a transfer to another word. This first set ofcheck signals is stored in memory with the selected word. Uponretrieval, a second set of check signals is generated for the addressand information bits of the selected word and the address of thepreceding word. The first and second sets of check signals are compared.Failure of the check sets to match indicates an error in the address,information or order of retrieval of the selected word.

BACKGROUND OF THE INVENTION Field of the invention This inventionrelates to data processing techniques and, more particularly, totechniques for ensuring the accurate and proper sequential order ofretrieval of information in a stored program machine.

A stored program machine or computer is typically characterized as onein which program instructions are stored in memory along with the dataon which the instructions operate. Frequently, such instructions takethe form of subroutines which are retrieved periodically, as requiredperhaps, by a master routine. The subroutines typically comprise anumber of steps or instructions, the first instruction of which will bereferred to as a transferee instruction, which must be performed inorder.

As a simple illustration, the master routine might be arranged tocompute the roots of the quadratic equation ax +bx+c for several sets ofdata. It is apparent that each solution for x requires the calculationof /4ac. Thus, the set of instructions for performing this square rootcalculation can be stored in the computer memory as a subroutine. Themaster routine then includes a transfer indication whenever the squareroot calculation is required and the square root subroutine is retrievedfrom memory in response thereto. Clearly, it is essential that thetransferee and subsequent instructions of the subroutine be correctlyaccessed since an impoperly accessed word will result in erroneousresults, or, at least, the loss of valuable computer time before theerror is detected.

In the type of system to which the present invention is applicable, eachword typically stored in digital form in memory occupies a locationhaving a unique address which is also typically represented in the formof a digital word.

A number of checking schemes have been employed in the prior art todetect the incorrect storing of such instruction Words. For example, acoded representation based on the information content of an instruction(or other) word is often generated at the time of storage and thisencoded representation is compared with another such representation uponretrieval of the word from memory. This coded representation often takesthe form of one or more parity bits which are appended to theinstruction data or other content of the word in question. The parity orcheck bits are then stored and retrieved with the remainder of the word.

The exact form and number of these parity bits varies, depending uponthe complexity (and therefore the error resolving power) of theassociated parity code employed. The details of these codes and thecircuitry for actually impiementing them are well known in the art andform no necessary part of the present invention. A useful referencedealing with such parity codes is Hamming Error Detecting and ErrorCorrecting Codes, Bell System Technical Journal, vol. 29, pp. 147-160,April 1950.

It is also well known in stored program systems to encode not only theinformation content of words stored therein, but to encode the addresscontent of those words also. Thus, data stored at incorrect addresses,as well as incorrect information bits, are readily detectable. (See, forexample, L. S. Tuomenoksa Pat. 3,231,858 issued Jan. 25, 1966.) However,these prior art schemes do not detect the erroneous retrieval of a wordhaving an entirely different (though internally consistent) address fromthe one intended since the information and parity portions of the wordretrieved are correct for the address accessed.

A different prior art technique, provides some protection againstimproper transfers within the memory. In accordance with this technique,a so-called transferallowed bit is appended to certain words in memoryto which a transfer may properly be made. However, since there are,characteristically, a number of such valid transferee words, althoughperhaps only a single correct one, an incorrect word having atransfer-allowed bit can still be accessed Without the error beingdetected. Such a system is described, for example, in F. S. VigliantePat. 3,283,307, issued Nov. 1, 1966 and assigned to the assignee of thepresent invention.

Accordingly, it is an object of the present invention to improve thereliability of stored program machines.

More particularly, it is an object of the present invention to detecterrors in the sequential retrieval of words stored in the memory of astored program machine. It is a related object of the present inventionto detect errors in the address and information content of those Wordsas well.

It is a still further object of this invention to reduce the storagefacilities required to provide such error detection.

BRIEF SUMMARY OF THE INVENTION In accordance with the preferredembodiment of the present invention, a code bit or bits (designated acode word) is associated with each word in a computer memory storageunit. Each such code word spans the information content of a given wordto which it is appended, the address of this given word and the addressof the word to be accessed immediately prior to the given word. Spanningin the present context is understood to mean encoding over thedesignated spanned information. Thus, in accordance with the techniquesof the present invention, information relating to the program sequence,as well as to the instruction (or other) words stored in memory and theaddress at which these words are stored is actually encoded and theresulting code words are stored in the memory unit.

It is therefore a feature of the present invention that encoding anddecoding circuitry be provided for generating code words based, in part,on the memory addresses of sequentially accessed instructions, includingin appropriate cases transfer and transferee words.

It is an additional feature of the present invention that the encodingcircuitry be arranged to span the content of a word to be stored in acurrently accessed memory location and to store a resulting code word ina portion of memory associated with the currently accessed memorylocation.

It is a further feature of the present invention that comparing means beprovided for comparing the code words generated by the encodingcircuitry upon retrieval of a word from memory and the code wordpreviously associated with the retrieved word.

A complete understanding of the present invention and of the above andother features and advantages thereof may be gained from a considerationof the following detailed description of an illustrative embodimentthereof presented hereinbelow in conjunction with the accompanyingdrawing in which:

FIGS. 1 and 2 depict the encoding and decoding portions, respectively,of an error detection system embodying the principles of the presentinvention;

FIG. 1A shows a typical storage pattern for the memory unit shown inFIGS. 1 and 2;

FIG. 2A illustrates the decoder of an alternate embodiment of thepresent invention; and

FIG. 3 shows a flow diagram of illustrative dynamic program sequences towhich the apparatus and techniques of the present invention areapplicable.

DETAILED DESCRIPTION An initial reference to FIG. 3 may prove helpful inacquiring an understanding of the operations involved in practicing thepresent invention. Shown in FIG. 3 are two program sequences, sequencesX and Y, which are typical of a broad range of such sequences commonlystored and executed in general (or special) purpose computers. SequenceY in FIG. 3- includes a conditional branc instruction which in typicalfashion reroutes the course of processing upon the satisfaction of aspecified condition. More will be said about this branching operationbelow. For present purposes only the sequential accessing ofinstructions (or other data) in, say, sequence Y need be considered.

In the normal course of processing sequence Y (with the conditionassociated with Word D unsatisfied), the words in sequence Y aredesirably accessed in the order B, D, F, and G. Accordingly, in usingthe most straightforward and commonly used techniques, the words B, D,F, and G will be stored in order in consecutive locations in thecomputer memory. Upon execution of sequence Y, then, all that isrequired is to repetitively increment the program counter commonly foundin computers. The apparatus of the present invention includes means toinsure that the incrementing of the program counter has been effectedcorrectly.

The purpose to be served by an encoder (such as that shown in FIG. 1) inaccordance with the present invention is to generate a code wordrepresentative of both the content and memory address of a currentlyprocessed word (e.g., G in FIG. 3). In accordance with a preferredembodiment of the present invention this code word is also arranged tobe representative of the address of the immediately preceding word inthe sequence of words being processed (e.g., F in FIG. 3 when the.curren Word accessed is G).

Referring to FIG. 1, then, there is depicted a source of informationsignals for generating digital words representing information or programinstructions to be stored in memory unit 20. Address generator 30generates signals identifying the location in memory unit at which theinformation signals are to be stored. Past address generator 35 respondsto the signals generated by address generator 30 to produce signalsrepresenting the address of the location which, according to the programroutine, is to be accessed immediately prior to the location whoseaddress is generated by address generator 30. Thus, as an informationsignal is generated by source It), its address is simultaneouslygenerated by address generator 30. In addition, past address generator35 generates the address of the location which will be accessed justbefore the address generated at address generator 30. Encoding network40 encodes these signals in accordance with a particular desiredencoding scheme. Endcoding network 40 typically comprises a Hammingencoder in accordance with the teachings of Gallager, Information Theoryand Reliable Communication, Wiley 1968 (especially chapter 6) and othertechniques well known in the art. Typical apparatus for generating therequired code signals is described further in e.g., U.S. Reissue Pat.23,601, issued Dec. 21, 1952 to R. W. Hamming et a1.

It will be assumed, for purposes of illustration, that each of thedigital words generated by a source 10 in FIG. 1 comprises 32 bits. Itis convenient for some purposes to consider these 32-bit words to beorganized into four 8-bit bytes. Each of these 8-bit bytes may be storedin a corresponding S-bit portion of a memory location in memory 20 asshown in part in FIG. 1A. These are indicated in FIG. 1A as bytes 1through 4. The portion of memory 20 indicated in FIG. 1A as byte 5 of,say location i, is typically reserved for the code word associated withthe information stored in bytes l-4 of location i, the address oflocation i and the address of the immediately preceding location.

It is also assumed for purposes of definiteness that the location of anygiven word in memory unit 20 in FIGS. 1, 1A and 2 is fully specified bya pattern of 8 bits. This, of course, applies to a current address, suchas i in FIG. 1A, as well as the preceding address, i-l (assuming atransfer instruction did not cause location i to become the currentaddress). Thus the check word stored in byte 5 of location i is onewhich is based on, or spans, the 32 bits of data to be stored inlocation i, the 8 bits of data associated with the address of location iand the address of the location for the immediately preceding 32-bitword processed by the system. Thus, each code or check word generated byencoding network 40 in FIG. 1 will be considered to comprise anadditional 8-bit byte. In short, then, these 8 check bits may beconsidered to form a parity word based on the associated information andaddress words comprising 32+8+8=48 bits.

After the information signals and addresses have been encoded, theinformation signals and code signals are stored in memory unit 20 at thelocation specified at address generator 39.

After being once stored in memory unit 20, the information and checkbytes are typically repetitively accessed as required during theprocessing of data in accordance with the stored program sequences. Uponeach accessing of, say, memory location i, a new encoding of theinformation stored at location i and of the address of location i andthat of the immediately preceding address is elfected. This process, byanalogy to the more common communication coding arts, will be referredto as decoding.

FIG. 2 illustrates the decoding apparatus of a preferred embodiment ofthe present invention. In accordance with FIG. 2, then, accessing unit45, under normal program control, generates successive addressesspecifying locations from which information signals stored in memoryunit 20 are to be read. Accessing unit 45 is functionally identical tothat found in most general purpose computers and other systems usingword-organized memories and can be easily implemented by an ordinaryworker in the art. In particular, design methods for such a circuit areincluded in Digital Computer Design Fundamentals by Yaohan Chu,McGraw-Hill Book Co., Inc., 1962, at chapter 12, sections 6 and 7.Alternatively, accessing unit 45 can comprise a programmed store forproducing the desired memory location address in response to externalstimulus. Program design for accomplishing this purpose is well withinthe skill of a worker in the art. See, for example, Microprogramming:Principles and Practices by Samir S. Husson, Prentice Hall, Inc., 1970.As information signals are read from memory unit 20, the address inaccessing unit 45 is replaced by the address of the next location to beaccessed and the first-mentioned address is shifted into delay unit 50.Thus, the address of each word accessed from memory unit 20 is availablein accessing unit 45 and the address of the location accessed justbefore it is stored in delay unit 50.

For each memory location accessed, decoding network 55 generates a codein the same manner described above for encoding network 40. Briefly, inaccordance with the encoding algorithm, decoding network 55 encodes theinformation signals from the currently accessed word in memory unit 20,the current memory address of those signals as read from accessing unit45 and the address of the previously accessed word stored in delay unit50.

Comparator 60 compares the code generated by encoding circuit 40 andstored with the information signals in memory with the code signalsgenerated by decoding network 55. A failure of the compared code signalsto match indicates an error in the information or address signals of theword accessed or, more importantly, the sequence in which the addresswas accessed. The signal generated by comparator 60 upon such a mismatchmay be used to stop program execution, to cause a transfer to anotherpoint in processing or otherwise follow an error control procedure,usually by means of special programs stored in memory 20.

The foregoing discussion describes apparatus used in a preferredembodiment of the present invention for checking programming sequences.The above-described embodiment of this invention is further adaptable tocheck program routines which include jump or transfer instructions.

Consider, for example, a simple jump or transfer instruction such asthat included in the dynamic sequencing routine illustrated in FIG. 3.

In accordance with this routine, sequence X includes instruction A, nodeC and instruction E. Similarly, sequence Y includes instruction B, nodeD and instructions F and G. As indicated in FIG. 3, node D is a socalledconditional branchpoint. That is, node D includes a conditional jumpinstruction which will cause one of a number of possible addresses (two,in this example) to be selected to designate the next instruction to beaccessed. This selection is made in standard fashion depending upon someproperty of one or more numerical expressions or other conditions(hence, the name, conditional branch).

With respect to node C, then, it is clear that, as it stands, there aretwo possible addresses corresponding to the immediately precedingaddress, that of instruction A and that of node D. That is, each ofthese addresses may properly precede the address of node C.correspondingly, there are two possible code words which may be storedin byte 5 of the location in memory corresponding to node C and whichmay be generated by decoding net- I work 55 upon accessing thislocation.

'0 or from node D to node C, the address of A is available as thepreceding address for calculating the comparison check word.

Apparatus in accordance with the present invention incorporating still adifferent arrangement for eifecting sequence checking of a systemcapable of executing jump instructions is depicted in FIG. 2A. As shownin FIG. 2A, a program store 110, operating through an instructionregister 120 and an instruction decoder 130 serves as a source ofinstructions which are executed by data registers (not shown) acting inconjunction with a data store (not shown). For simplicity, the programstore is a separate unit from the data store, but the same unit, forexample, a magnetic core matrix of well-known construction may be usedfor both. In addition, the various constituent gates, registers, anddecoders of the figure are of standard design.

Before an instruction can be executed, it must be taken out of storage.This is done by a program address register 140 whose coded output givesthe location of the instruction in the program store 110. After the codesignals forming the address are gated in parallel through a programaddress gate 151 to the program store, the associated instruction passesthrough a preliminary register gate 152 into the instruction register120. Both gates 151 and 152 are enabled from a timing network (notshown) of conventional construction. The instruction entering theregister conventionally has two portionsa coded command that enters afirst section 121 of the register 120 and a coded address that enters asecond section 122 of the register 120. The command is translated by thedecoder 130, which is operated by the timing network; the address isdispatched to the data store and registers.

Under ordinary circumstances, where the steps of the program follow insequence, by accessing consecutive memory locations, each succeedingaddress at the output of the program address register 140 is obtained byaugmenting its predecessor by unity through the operation of a standardincrement circuit 141 and an increment circuit gate 142. However, when atransfer is to take place, the address indicated by the program addressregister 140 must be modified to accord with the location in the programstore 110 of the first instruction to which a transfer is to be made.This modification is carried out through the use of a transferinstruction whose address portion does not refer to a location in thedata store, but rather to a transfer location in the program store. Whenthe transfer instruction enters the register 120, the decoder operates atransfer gate 143, causing the transfer address in the register 120 toenter the program address register where the preexisting address iseither replaced or modified. In that event, the next instructionentering the register 120 should be the first, i.e., transferee,instruction of a subset to which a transfer is being made.

To provide an indication of whether or not the transfer takes placeproperly, the invention provides for a delay unit 150, which typicallycomprises a shift register, for storing the address of the immediatelypreceding accessed word. When no jump instruction is encountered theoperation of the system is as shown in FIG. 2 and described above. Jumpcontrol circuit 170 is arranged to respond to a jump or transferindication being stored in the command portion 121 of instructionregister 120 to change the address stored in delay unit to anappropriate value associated with the address portion 122 of instructionregister 120. Again, jump control circuit 170 can be either a circuitdesigned in accordance with the Chu reference cited above or a programformulated in accordance with the above-cited Husson reference. In thelatter instance jump control circuit 170 comprises a microprogram storeaddressed by the address portion 122 of instruction register 120 asgated by gate in response to a signal from the instruction decoder 130indicating that a jump instruction such as D in FIG. 3 is present. Themicroprogram store then responds with the memory address for theinstruction A. Thus in accordance with the alternate embodiment of FIG.2A there is provided circuitry which, in response to the con- 7 ditiongiving rise to the jump transfer, forces the address of D to be changedto that of A.

Decoder 155 in FIG. 2A is of the same type as that used in the circuitindicated by the block 55 in FIG. 2. The inputs to decoder 155 are onceagain the current and preceding addresses and the information stored inthe currently accessed Word. This latter information is seen to'includecommand and address portions, corresponding to the contents of registers121 and 122, respectively. The output of decoder 155, in common with theoperation of the equivalent circuitry of FIG. 2, is delivered tocomparator 160 as is the parity portion of the current Word stored inparity register 123.

While the detailed explanation of the alternate embodirnent of FIG. 2Ahas emphasized the decoding (that is, the comparison of present and pastencoding of the memory contents and the various addresses), it is clearthat equivalent techniques may be used for determining the parity wordsto be stored at each memory location.

It should be understood that the above-described arrangements areillustrative only. Numerous other arrangements may be devised by thoseskilled in the art without departing from the spirit and scope of theinventron. For example, it is clearly within the spirit and scope of thepresent invention that the contents of the foregoing word be encodedwith the contents and address of the succeeding word rather than theaddress of that foregolng Word. Similarly, other combinations ofinformation bits included in the predecessor word and the successor Wordencoded to yield a check on the sequence of retrieval are again withinthe scope of the present invention. It is also clear in light of thepresent invention, as disclosed herein, that sequences of more than twowords can be thus encoded. For instance, the addresses of two precedingwords can be encoded with the address of a third. It is also apparentthat coding techniques, other than the parity scheme described withrespect to the preferred embodiment, can be used to achieve greaterreliability.

It should be further understood that the byte and word lengths given inthe foregoing description are merely illustrative. Similarly, theaddress-indicating words are not necessarily limited to 8 bits or anyother length. If for any reason 8-bit address words are convenient forencoding purposes, it is sometimes convenient to use only the low order8 bits in a larger address-specifying field.

In some realizations of the present invention it may be desirable toprovide separate byte stores for each of the columns of bytes of thetype shown in FIG. 1A. When this is the case, and where separate addressdetermining circuitry is used for each byte memory, additionalreliability is introduced because the likelihood of an identicalaccessing error being made at the same by more than one byte store isquite unlikely.

What is claimed is:

1. In a system having a memory for storing a plurality of program anddata words, apparatus responsive to signals from said memory for storingfor detecting an error in the content or sequencing of a plurality ofsaid words accessed from said memory comprising:

(A) means for generating for [each] a given word stored in said memory afirst code word representative of the information content of [that] saidgiven Word, and of the location at which [that] said given word isstored in said memory and of the location of a difierent word desired tobe accessed in accordance with a predetermined ordered relationship to[that] said given Word,

(B) means for storing said first code Words,

(C) means forretrieving the code word associated with a given program ordata word upon the accessing of said given word,

(D) means for generating for the program or data word most recentlyaccessed from said memory a second code word representative of theinformation content of [that] said most recently accessed word, and ofthe location from Which Ethat] said most recently accessed word wasaccessed, and of the location from which a Word bearing saidpredetermined ordered relationship to said most recently accessed wordwas accessed, and

(E) means for generating an error signal whenever the first and secondcode words associated with an accessed word do not bear a predeterminedrelationship to each other.

2. Apparatus according to claim 1, wherein said means for generating anerror signal comprises a comparator arranged to generate an outputsignal whenever said first and second code words are difierent.

3. Apparatus according to claim 1, wherein said means for generatingsaid first code Words and said means for generating said second codeWords each comprises a parity check circuit.

4. Apparatus according to claim 3, wherein said means for generatingsaid first code words further comprises means for selecting the wordintended to be accessed immediately prior to the word Whose informationcontent is represented by said first code word as said word intended tobe accessed in accordance With said predetermined relationship.

5. Apparatus according to claim 4, wherein said means for generatingsaid second code words comprises means for selecting the location of theword actually accessed immediately prior to said most recently accessedword as the location of said word bearing said predeterminedrelationship to said most recently accessed word.

6. Apparatus according to claim [4] 5, wherein said means for selectingin said means for generating said sec ond code words comprises means forstoring the address of the location from which a most recently accessedWord was accessed until after the following word is accessed from saidmemory, and means for applying said stored address to said parity checkcircuit in said means for generating said second codewords. v

7. In a system having a memory for storing a plurality of program anddata words, apparatus responsive to signals from said memory for storingfor detecting an error in the content or sequencing of a plurality ofsaid words accessed from said memory comprising (A) means for generatingfor a given word stored in said memory a first code word representativeof the information content of said given word, and of the location atwhich said given word is stored in said memory and of a characteristicof a word desired to be accessed in accordance with a predeterminedordered relationship to said given word,

(B) means for storing said first code words,

(C) means for retrieving the code word associated with a given programor data word upon the accessing of said given word,

(D) means for generating for the program or data word most recentlyaccessed from said memory a second code word representative of theinformation content of said most recently accessed word, and of thelocation from which said most recently accessed word was accessed, andof a characteristic of a word bearing said predetermined orderedrelationship to said most recently accessed word, and

(E) means for generating an error signal whenever the first and secondcode words associated with an accessed word do not bear a predeterminedrelationship to each other.

8. In a system having a memory for storing a plurality of program anddata words, apparatus responsive to-signals from said memory for storingfor detecting an error in the content or sequencing of a plurality ofsaid words accessed from said memory comprising (A) means for generatingfor a given word stored in said memory a first code word representativeof the information content of said given word, and of the location atwhich said given word is stored in said memory and of the informationcontent of a different word desired to be accessed in accordance with apredetermined ordered relationship to said given word,

(B) means for storing said first code words,

(C) means for retrieving the code word associated with a given programor data word upon the accessing of said given word,

(D) means for generating for the progrm or data word most recentlyaccessed from said memory a second code word representative of theinformation content of said most recently accessed word, and of thelocation from which said most recently accessed word was accessed, andof the information content of a word bearing said predetermined orderedrelationship to said most recently accessed word, and

(E) means for generating an error signal whenever the first and secondcode words associated with an accessea' word do not bear a predeterminedrelationship to each other.

patent.

References Cited The following references, cited by the Examiner, are 5of record in the patented file of this patent or the original UNITEDSTATES PATENTS Tuomenoksa et a1.

CHARLES E. ATKINSON, Primary Examiner

